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MP6900 fast turn-off intelligent controller MP6900 rev. 1. 12 www.monolithicpower.com 1 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. the future of analog ic technology descri ption the mp69 00 is a low-drop, fast turn-off intelligent controller th at combined with an external switch repla c e s schottky diodes in high-efficien cy, flyback converters. the ch ip regulates th e forward drop of an ext e rnal switch to about 70mv and swi t ches it off as soon a s the voltage becomes negative. package choices are a space saving tsot 23-5, qfn6 (3x3mm) or soic-8. features ? works with both standard and logic level fets ? compatible with energy star, 1w standby requiremen ts ? v dd range from 8v to 24v ? fast turn-of f total dela y of 20ns ? max 400khz switching f r equency ? <3ma low quiescent current ? supports ccm, dcm a nd quasi-resonant topologies ? supports high-side and low-side rectification ? power savi ngs of up to 1.5w in a t y pical notebook adapter appli c ations ? industrial po wer syste m s ? distributed power systems ? battery powered systems ? flyback converters all mp s pa r t s ar e l e ad- fre e and a d h e r e to th e r o hs d i r e ctiv e. fo r m p s g r e e n st atus, p l e a se vi si t mp s we bs ite un d er pro d u cts, q u a l it y ass u r a nce pa ge . ?mp s ? an d ?t he f u ture o f ana l o g ic t e chno lo gy ? ar e re gi ste r ed tr ade ma r ks o f monolithic power systems, inc. typical application http://
MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 2 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. ordering information part number package top marking MP6900dj* tsot23-5 6d MP6900ds** soic-8 MP6900ds MP6900dq*** qfn6 (3x3mm) 5d * for tape & reel, add suffix ?z (e.g. MP6900dj?z). for rohs compliant packaging, add suffix ?lf (e.g. MP6900dj?lf?z) ** for tape & reel, add suffix ?z (e.g. MP6900ds?z). for rohs compliant packaging, add suffix ?lf (e.g. MP6900ds?lf?z) *** for tape & reel, add suffix ?z (e.g. MP6900dq?z). for rohs compliant packaging, add suffix ?lf (e.g. MP6900dq?lf?z) package reference t o p view v g v ss v dd 1 2 3 5 4 pgnd v d marking pgnd en nc v d v g nc v dd v ss 1 2 3 4 8 7 6 5 t op view tsot23 -5 soic-8 qfn 6 (3x 3 m m ) absolute m a xi mum ratings (1) v dd to v ss ...................................... -0.3v to +27v pgnd to v ss ................................ -0.3v to +0.3v v g to v ss ......................................... -0.3v to v cc v d to v ss ..................................... -0.7v to +180v en to v ss ..................................... -0.3v to +6.5v maxi mum operating fre quency............. 400khz continuous power dissipation (t a = +25c) (2) soic8 ...................................................... 1.39w tsot23-5 ................................................ 0.57w qfn6 (3 x3mm) .......................................... 2.5w junction te mperature ............................... 150 c lead temperature (solder)....................... 260 c storage temperature .............. -55c to +150 c recommended operation conditions (3) v dd to v ss ............................................ 8v to 24v operating junction temp. (t j ) . ... -40c to +125c thermal resistance (4) ja jc soic8 ..................................... 90 ...... 45 ... c/w tsot23-5 .............................. 220 .... 110 .. c/w qfn6 (3 x3mm) ....................... 50 ...... 12 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the maximum junction temperatu r e. t j (max) the junction-to- ambient thermal resistance ja a nd the ambient temperatu r e t a . the ma ximu m allow able po w e r dissipation at an y ambient temperatu r e is calculated using: p d (max)=(t j (ma x )-t a )/ ja . exceeding the maximum allo wable po w e r dissipation w ill cause ex cessive die temperature, and the regulator w ill go into thermal sh utdo w n . inte rnal thermal shutdo w n circuitr y protects the device from perma ne nt damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 3 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. electri c al characteristi cs v dd = 12v, t a = +25 c, unless otherw ise noted . parameter conditio n s min t y p max units v dd voltage ran ge 8 24 v v dd uvlo ri sing 5.0 6.0 7.0 v v dd uvlo hystere s i s 1.2 v operating cu rre nt c load =5nf, sw =100kh z 8 12 ma quie scent current no switching 2 3 ma shutdown cu rre nt v dd =4 v 100 150 a v dd =20v en= 0 v (50k ) 250 a therm a l shut down 170 o c therm a l shut down hystere s is 50 o c enable (lo w ) soic-8 o n ly 0.8 v enable (high ) soic-8 o n ly 2 v pull-up curre n t on enable soic-8 o n ly 5 10 a control circuitry section v ss ?v d forward voltag e, vfwd 55 70 85 mv c load = 5nf 150 ns turn -on dela y c load = 10nf 200 ns pull-do wn re sista n c e of v g pin 10 20 k input bias cu rre nt on v d pin -0.3v > v d >1 80v 10 a minimum on-time c load = 5nf 200 ns gate driver section v g (low) i load =1ma 0.05 0.5 v v dd >17v 12 13.5 15 v v g (high ) v dd <17v v dd -2.2 turn -off thr e shol d (v ss -v d ) 20 30 40 mv turn -off prop agation delay v d =v ss , r gat e =0 15 ns v d =v ss , c loa d =5nf, r gat e =0 20 35 ns turn-off total delay (5) v d =v ss , c loa d =10n f, r gat e =0 30 45 ns pull-do wn im peda nce 1 2 pull-do wn cu rre nt 3v MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 4 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. pin functio n s tsot23 -5 pin # soic8 pin # qfn6 (3x3mm ) pin # nam e des c ription 1 8 6 vg gate drive output 2 5 4 vss ground, also used as reference for vd 3 6 5 vdd supply voltage 4 4 3 vd fet drain voltage sense 5 1 1 pgnd power ground, return for driver switch - 2 2 en enable pin, active high - 3 nc no conn ectio n - 7 nc no conn ectio n
MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 5 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. typical perfo r manc e characteristics v dd = 12v, unless otherwise noted. v fwd vs. t e m p er at u r e -50 0 50 100 150 v fwd (mv) tur n of f t hr e s hol d v s . t em p er at u r e -4 0 -3 5 -3 0 -2 5 -2 0 -50 0 50 100 150 tur n of f t hre s hold ( v) q u i escen t c u r r en t vs. temper at u r e 1 1. 2 1. 4 1. 6 1. 8 2 2. 2 2. 4 -50 0 50 100 150 q u i escen t cu r r en t ( ma ) shutdown current vs. te m p er at u r e 50 100 150 200 - 50 0 50 100 150 5 5. 5 6 6. 5 7 - 5 0 0 50 100 150 v dd uv l o ri s i n g ( v ) v dd uvlo rising vs. temperature v ds 50v/div v gs 5v/div i sd 10a/div operation in 90w flyback application (5) (v in =90vac, i out =1a) operation in 90w flyback application (v in =90vac, i out =4.7a) v ds 50v/div v gs 10v/div i sd 10a/div operation in 90w flyback application (v in =250vac, i out =1a) v ds 50v/div v gs 5v/div i sd 10a/div operation in 90w flyback application (v in =250vac, i out =4.7a) v ds 50v/div v gs 10v/div i sd 10a/div 60 65 70 75 80 notes : 5) see fig.7 for the test circuit..
MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 6 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. block diagram figure 1?functional block diagram operation the mp690 0 supports operation in ccm, dcm and quasi-resonant topologies. operating in either a dcm or quasi - resonant topology, the control circu i try controls the gate in f o rward mode and will turn the gate off when the mosfet current is fa irly low. in ccm operatio n, the contro l circuitry turns off the gate whe n very fas t transients o ccur. blanking the control circuitry con t ains a b l an king fun c tio n . when it pulls the mosf et on/off, it makes sur e that the on/ off state at least last s fo r some time. the turn o n blanking time is ~ 1 .6us, which determines the minimu m on-time. du ring the turn on blanking period, the turn off threshold is n o t totally blan ked, but changes t he thresho l d voltage to ~+50mv (i nstead of -30mv). th is assures tha t the part can always be turned off even during the turn on blanking p e riod. (albeit slower, so it is not re commended to set the synchronous period le ss than 1. 6us at ccm condition in flyback converter, oth erwise shoot through may occur) vd clamp because v d can go a s high as 1 80v, a hig h - voltage jf et is u s ed at the inp u t. to avoid excessive currents when vg goes b e low -0.7v, a small resist or is re commended between v d and the drain of t he external mosfet. under-voltage lockout (uvlo) when the vdd is below uvlo thres hold, the par t is in sleep mode and the vg pin is pu lled low by a 10k resi st or. enable pin the enable function is only a v ailable on the soic-8 package. if en is pulled low, the part is in sleep mode.
MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 7 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. thermal shutdow n if the junction temperat ure of the chip exceeds 170 o c, the vg will be pulled low and the par t stops switching. the part will return to normal function af t e r the jun c tion temp erature ha s dropped to 120 o c. thermal design if the dissipation of t he chip is higher than 100mw du e to switching frequencies above 100khz, v dd higher than 15v and/or cload larger than 5nf, it is recommende d to use the thermally-en hanced soic-8. turn-on ph ase when the synchronous mosfet i s conductin g , current will flow throu gh its body diode which generates a negative vds across it. because this body diode voltage drop (<-500mv) is much smaller than the turn on threshold o f the control circuitry (-70mv), whic h will then pull the gat e driver volta ge high to turn on the synchronous mosfet after about 150ns tu rn on delay (defined in fig.2). as soon a s the turn on threshold (-70mv) is triggered, a blanking t i me (minimum on-time : ~200ns) will be added during which the turn off threshold will be change d from -30mv to +50mv. this blankin g time can help to avoid error trigger on turn off threshold caused by the turn on ringing of th e synchronous mosfet . v ds v gate t don t doff -7 0 m v -3 0 m v 2v tot a l t 5v figure 2?turn on and turn off dela y conducting phase when the synchronous mosfet is turned on, vds beco m es to rise according to its on resistance , as soon as vds rises a bove the turn on threshold (-70mv), the control circuitry sto p s pulling up t he gate dr i v er which l eads the g ate voltage is p u lled down by the inter nal pull-dow n resistance ( 10k ? ) to lar ger the on resistance o f synchronous mosfet to ease th e rise of v d s. by doing that, vds is adjusted to be around - 70mv even when the current through the mos i s fairly small, this function can ma ke the driver voltage fairly low when the synchronous mosfet is turned off t o fast t he t urn off sp ee d (this functio n is still act i ve during tu rn on blankin g time which means the gate driver could still b e turned off even with very s m all duty of the synchronous mosfet). turn-off ph ase when vds r i ses to trigg er the turn o ff threshold ( - 30mv), the gate volta ge is pulle d to low af ter about 20ns t u rn off delay (defined in fig.2) by the control circuitry. similar with turn- on phase, a 200ns bla nking time is adde d after the synchronous mosfet i s turned off to avoid error trigger. fig.3 shows synchronous rectification operatio n at heavy loa d condition. due to the high current , the gate dri v er will be saturated at f i rst. after v d s goes to a bove -70mv, gate dr iver voltage decreases t o adjust the vds to typical -70mv. fig 4 shows synchrono us rectification operatio n at light load condition. d ue to the low current, the gate driver voltage never saturates but begins to decrease as soon as th e synchronous mosfet is turned on and adjust t he vds. -70 m v -30 m v vds isd vg s t 0 t1 t2 figure 3?synchronous rectification operation at heavy load
MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 8 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. -70mv -3 0 m v vd s is d vg s t0 t1 t2 figure 4?sy nchronou s rectification operation a t light load sr mosfet selection and driver a b ility the power mosfet sele ction proved to be a trad e off between ron and qg. in order to achieve hig h efficiency, t he mosfet with smaller ron is always preferred, while the qg is usually larger with smaller ron, which mak e s the turn-on/off spee d lower and lead to larger power loss. for MP6900 , because vd s is regu lat ed at ~-70mv during the driving period, the mosfet with too small ron is not recommend, because the gate driver ma y b e pulled down to a fairly low level with too small ron when t he mosfet current is still fairly high, which make the advantage of the low ron inconspicuo u s. fig.5 shows the typical waveform of qr fl yback. assume 50% duty cycle and the o u tput curren t is i out . to achieve fairly high usage of the mosfet?s ron, it is expected that the m o sfet be fu lly turned on at least 50% of the sr conduction period: vfwd ron i ron ic vds out ? ? ? = ? = 2 where v ds is drain-source voltage of the mosfet and v fw d is the forward voltage threshold o f mp6902, wh ich is ~70m v. so the mosfet?s ron is recommen ded to be n o lower than ~35/i out (m ). (for example, for 5a application , the ro n of the mosfet is recommend ed to be no lower than 7m ) fig.6 shows the corresp onding total delay during turn-on per iod (t tot a l , see fig.2) with driving different qg mosfet by mp6902. from fig.6, with driving a 12 0nc qg mosfet, the dri v er ability o f MP6900 is able to pull up the gate driver voltag e of the mosfet to ~5v in 300ns as soon as th e body diode of the mo sfet is cond ucting, which greatly save the turn -on power loss in t h e mosfet?s bo dy diode. id i pea k vg sr conduction period 50 % s r c on duc t i on p e r i od ic i p eak ? 4 i ou t ic ? 2 i ou t figure 5?sy nchronou s rectification ty pical w a v e forms in qr fl y b a ck t u rn -o n d e l a y v s . q g 0 50 10 0 15 0 20 0 25 0 30 0 35 0 0 2 0 4 0 6 0 80 100 1 20 1 40 qg ( n c ) t ot a l d ela y ( n s ) figure 6?total turn-on dela y vs. q
MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 9 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. typical application circui t p g n d p g n d p g n d 1 k r 1 0 p g n d 2 0 k r 7 n c r f 1 3 9 0 p c 1 5 5 1 k r 1 6 2 2 u f / 2 5 v c 1 1 t l 4 3 1 u 2 2 0 k r 2 3 a g n d 1 0 k r 2 8 1 0 0 n f c 1 6 2 k r 2 6 6 6 . 5 k r 2 7 a g n d n a r 2 9 1 m r 2 1 o h m s r 3 1 o h m s r 4 1 0 k r 1 2 1 5 0 k r 1 1 4 . 7 n f / 1 k v c 1 0 1 0 0 u f / 2 5 v c 1 4 0 . 1 u f / 2 5 v c 1 2 n c r 1 8 1 k r 2 4 n c c 8 1 u f / 5 0 v c 9 5 o h m s r t 1 2 2 p f c 1 3 1 0 n f c 5 0 . 2 2 u f / 2 5 0 v a c c x 1 u s 1 k - f d 2 1 m r 1 0 r 2 5 5 0 r 1 9 n c r 2 1 1 a f 1 1 1 c n 1 1 . 5 o h m s r 5 1 2 4 3 g b u 4 j b d 1 1 5 0 k r 1 3 a p 2 7 6 1 i q 1 2 4 2 4 m h l x 1 2 . 2 n f / 2 5 0 v a c c y 3 n c r 2 0 4 3 1 2 p c 8 1 7 b u 3 4 . 7 n f / 2 5 0 v a c c y 1 1 1 c n 2 4 . 7 n f / 2 5 0 v a c c y 2 c o m p 4 f s e t 5 g n d 3 v c c 6 s o u r c e 2 n c 7 d r v 1 h v 8 h f 0 2 0 0 v s v d v s s 5 v g 8 v d 4 n c 7 n c 3 p g n d 1 e n 2 v d d 6 m p 6 9 0 0 d s u 1 n c n c 1 n c r 6 v s v d 1 0 k r 1 5 d 4 1 k r 1 7 1 0 r 9 d 5 2 0 r 2 2 m 1 d 7 1 0 0 0 u f c 6 2 2 0 u f c 7 d 3 1 0 r 1 4 d 1 q 2 v g v g 1 u f c 4 1 0 0 u f c 1 1 1 1 3 8 1 0 3 1 6 4 t 1 4 5 : 9 : 7 : 7 e e 2 8 _ l p g n d a g n d a g n d v a u x v a u x figure 7?MP6900 for secondary sy nchrono us controller in 90w fl y back app lication
MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 10 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. package informati o n tsot23-5 0.30 0.50 seating plane 0.95 bsc 0.84 0.90 1.00 max 0.00 0.10 top view front view side view recommended land pattern 2.80 3.00 1. 5 0 1.70 2.60 3.00 1 3 4 5 0.09 0.20 note : 1) a ll d imensions ar e in mil l imet e r s. 2) pac kage len g t h does not incl u de mold flash, protr u sion or gate b urr. 3) pac k age widt h does not in clu d e int e rlea d fl ash or protrusion. 4) l e ad c o pl ana rity (bott om of lead s aft e r formi ng) shall be 0.10 millimeters max. 5) d rawing conf orms to jedec mo-193, va riat ion aa. 6) drawing is not to scale. 0.30 0.50 0 o -8 o 0.25 b s c gauge plane 2.60 typ 1.20 typ 0.95 bsc 0.60 typ see detail "a" detail a
MP6900- f a s t t urn- off intelligent con t rolle r MP6900 rev. 1. 12 www.monolithicpower.com 11 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. soic8 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0. 0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0 . 013(0 .33) 0 . 020(0 .51) seating plane 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.0 53(1.3 5) 0.069(1.75) top view front view 0.228(5.80) 0.244(6.20) side view 14 85 recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) note: 1) cont rol d i mension is in in ches. d imension in bra cket is in millimeter s . 2) pac kage len gt h does not in cl ude mold fl ash, protru sion s or ga te bu rrs. 3) pac kage width does not in clu de int e rlea d fl ash or protru sion s. 4) l e a d copla nar ity (bottom of l e ads a f t e r formin g ) shal l be 0 . 004" in ches max. 5) dr awing conf or ms to jedec ms-012, va riat ion aa. 6) dr awing is not to scale. 0.010(0.25) bsc gauge plane
MP6900- f a s t t urn- off intelligent con t rolle r notice: t he i n formatio n in this docum ent i s subject to chang e w i t h o u t notice. users sh oul d w a rra nt and gu arante e that third part y int e ll ectu al prop ert y r i g h ts are n o t inf r ing ed u p o n w hen i n tegr atin g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. MP6900 rev. 1. 12 www.monolithicpower.com 12 9/19/2012 mps proprietar y information. pate nt protected. pat ent protected. u nauthorized phot oc op y and duplication prohibited. ? 2012 mps. a ll rights reserved. qfn6 (3x3mm) side view top view 1 6 4 3 bottom view 2.90 3.10 1.40 1.60 2.90 3.10 2. 20 2.40 0.95 bsc 0.35 0.45 0.8 0 1.00 0.00 0.05 0.20 ref pi n 1 i d m a rki ng 1.50 0.95 0.40 recommended land pattern 2.90 note: 1 ) a l l di me ns i o ns are i n m i l l i m e t e r s . 2) exposed paddle size does not include mold flas h . 3 ) l e ad co p l an ari t y s h a l l be 0. 1 0 mi l l i m e t e r ma x . 4 ) j e de c r e f e re nce i s m o - 2 2 9 , v ar i a t i o n v e e a - 2 . 5 ) d r a w in g is n o t t o s c a l e . pi n 1 i d see detail a 2. 30 0. 80 pin 1 id option a r0.20 typ. pi n 1 id o p t i o n b r0 . 2 0 t y p . detail a 0.35 0.55 pin 1 id index area

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